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8bit.详细的八位十六进制频率计课程报告
- 详细的八位十六进制频率计课程报告，是我的eda课程设计报告书,Detailed eight hexadecimal Cymometer curriculum report is my report on the curriculum design EDA
CPU
- 从C语言到CPU的指令设计，设计了一个基本的CPU指令集-From the C language to CPU instruction design, the design of a basic CPU instruction set
jisuanjizucheng3
- 计算机组成原理课程设计。基本模型机的设计—跳转、转移指令的实现 熟悉微程序控制的原理，掌握微程序的编制、写入并观察运行状态。明白每一条指令在内存、CPU中的存取和执行流程-Principles of curriculum design computer components. The basic model design- Jump, the realization of the transfer of command are familiar with the principle of mic
alu8bit
- alu8bit.Usefull in design simple CPU(for beginner)
cpudesignvhd
- 内包含在VHDL环境下的CPU设计原理图和代码以及最后的仿真过程-Within the VHDL environment is included in the CPU design schematics and code, as well as the final simulation
simplecpu
- It s about design a simple cpu
cpudesign
- Risc 32位CPU设计方法，由牛人主讲，可以好好学习-Risc 32 Wei CPU design methodology, from the cattle were speakers, you can learn
CPU
- 介绍如何运用VHDL设计CPU。并且简单介绍了CPU的内部结构与功能-Describes how to use VHDL design CPU. And a brief introduction of the CPU' s internal structure and function
CPU
- 一個CPU之設計與實作 - 使用FPGA實作-CPU Design Practice
FPGA-cpu
- 基于FPGA的简易处理器设计2010/05/04-A simple FPGA-based processor design 2010/05/04
Ship_based_on_dual_CPU_design_generator_protection
- 基于双CPU的船舶发电机保护测控装置设计Ship based on dual CPU design generator protection and monitoring device-Ship based on dual CPU design generator protection and monitoring device
CPU-IC
- CPU卡一些资料，CPU IC卡系统通讯协议及底层程序的设计，CPU卡详解-CPU card with some information, CPU IC card system communication protocol and the underlying process of design, CPU card Detailed
mips--cpu
- 本文基于32位 MIPS CPU的体系架构，采用Xilinx ISE 9.1i软件，通过使用Verilog语言编写了32位MIPS单周期和多周期CPU的程序，完成了其逻辑设计并进行了仿真测试。-Based on a 32 MIPS CPU architectures using the Xilinx ISE 9.1i software, write a 32-MIPS, single cycle and multi-cycle CPU program completed its logic de
cpu_VHDL_
- 简单的CPU设计，基于VHDL语言的COA课程设计报告，含源代码及仿真文件等-simple cpu design , based on VHDL
CPU
- CPU设计时间报告，VHDL含有详细代码，下载到实验台后能用-Can be used after the the CPU design time report, VHDL contains detailed code downloaded to the bench
lab-1-ALU-design-with-Verilog-HDL
- cpu设计的运算器部分verilog代码，实验资料，包括原理和代码，在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
lab-4-cpu-design-with-Verilog-HDL
- 用veriloghdl 编写的cpu代码，modusim仿真通过，包括原理图和代码，以实验报告形式写出-CPU code, written in veriloghdl modusim simulation through, including the principle diagram and code, in the form of a lab report write
CPU
- 基于FPGA控制的ASIC CPU系统设计，全是用VERILOG代码编写，可以做加减乘除运算 -FPGA-based control ASIC CPU system design, all made with VERILOG code writing, arithmetic operations can be done
CPU
- 我是2014级复旦的研究生。这是一个8位的CPU设计VHDL实现。本CPU基于RISC架构，实现了cpu的基本功能如：加减乘除运算，跳转等。此外，里面有一个17位的ROM区，是存储指令的。你可以写出一段17位的指令代码，并放入ROM区，该CPU即可自动运行出结果。压缩包里是源代码和我们当时的设计要求。本源代码的最后调试时在地址0 17是放入的斐波纳契数字(Fibonacci Numbers)指令。通过modelsim仿真即可看到结果。-I am a 2014 graduate of Fudan
CPU
- 设计实现cpu，组成合理计算机系统,从硬件到软件，统统自己动手(Design and implement CPU, make up a reasonable computer system)